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Texas Instruments SN74F30N — Microcontrollers & Processors (MCU / MPU / DSP)

Texas Instruments SN74F30N 8-Input NAND Gate, 14-DIP, 5ns

MPNSN74F30N
End of Life

Texas Instruments 74F series NAND Gate, SN74F30N, single 8-input, 14-DIP (0.300", 7.62mm), through-hole, 4.5V–5.5V supply, 5ns propagation delay, ROHS3 compliant.

$0.69Ref. price · indicative, final on quote
Packaging14-DIP (0.300", 7.62mm)
RoHSROHS3 Compliant
Series74F
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74F30N specifications
ParameterValue
Series74F
Logic typeNAND Gate
MountingThrough Hole
Supply voltage4.5V ~ 5.5V
Current - quiescent1.5 mA
Current - output high, low1mA, 20mA
I/O channels8
Operating temperature0°C ~ 70°C
PackageTube
Case14-DIP (0.300\", 7.62mm)
Number of circuits1
Input logic level - low0.8V
Input logic level - high2V
Max propagation delay @ v, max CL5ns @ 5V, 50pF

Product details

Single 8-input NAND in a 14-pin DIP

The SN74F30N is a single 8-input NAND gate from Texas Instruments' 74F series, packaged in a 14-pin DIP (0.300" width, 7.62mm pitch). It performs the NAND logic function on eight inputs and outputs a single result — useful for wide-input decode, parity generation, or combining multiple sensor signals into one interrupt line.

5ns propagation delay sets the timing budget

Maximum propagation delay is 5ns at 5V supply with a 50pF load. At a 5V rail, this is the ceiling for data-to-output valid time — a downstream latch or counter clocked at 100 MHz sees a 5ns gate delay as half a clock period, so the input setup must account for it. The 74F family uses Schottky clamping to keep the delay short without the power penalty of full Schottky TTL. Output drive is asymmetric: 1mA source (logic high) and 20mA sink (logic low). The high-side fan-out is limited to about 10 standard 74F loads; the low side can drive 20 or more. If the gate feeds a long trace or a high-capacitance input, the rise time on the high-going edge will be slower than the fall — a consideration for bus-hold or line-termination planning. For a single gate this is modest — the 74F series draws more standby current than 74HC or 74LVC, but the speed justifies it. The commercial temperature grade (0°C to 70°C) limits this part to indoor, non-condensing environments.

Through-hole DIP for legacy or prototype boards

The 14-DIP package (0.300" body width, 7.62mm lead pitch) is a through-hole footprint that dates back to the original TTL era. It suits socketed prototypes, hand-assembly runs, or rework of legacy boards where a surface-mount gate would require a new layout. The 0.100" pin spacing is breadboard-compatible. Input logic thresholds are TTL-compatible: low at 0.8V max, high at 2V min. This means the gate interprets a 0V–0.8V signal as logic low and a 2V–5.5V signal as logic high — standard for 5V TTL families. No level translation is needed when driving from another 5V TTL or 3.3V CMOS with a pull-up to 5V.

Active production, ROHS3, no obsolescence watch

ROHS3 compliant (lead-free, no exempt substances) — no need to chase a RoHS exemption expiry or stockpile legacy inventory. Sourced to order against BOM quantities. No stock-holding claim — each lot is verified for marking consistency and date-code traceability before shipment.

Frequently asked questions

How can I order the SN74F30N or check availability?

The SN74F30N is sourced to order against your BOM quantity. Submit an RFQ for lot traceability and date-code verification.

Will the SN74F30N drop into a board designed for the SN74F00DR?

No. The SN74F00DR is a quad 2-input NAND in a surface-mount SOIC package with a different pinout. The SN74F30N is a single 8-input NAND in a through-hole 14-DIP. The logic function and package are completely different — a board spin is required.