Dual JK flip-flop with preset and reset
The SN74F112N is a dual JK flip-flop from the 74F series, each element containing one bit with set (preset) and reset inputs. It triggers on the negative edge of the clock, and the outputs are complementary — Q and Q-bar are available on adjacent pins. This means the flip-flop can latch data within 6.5 ns of the clock edge, setting the timing budget for the downstream logic.
Supply, drive, and temperature envelope
The output can source 1 mA and sink 20 mA — enough to drive a standard TTL load or a low-power LED through a series resistor.
Through-hole DIP package and board fit
Housed in a 16-pin DIP with 0.300-inch (7.62 mm) row spacing, the SN74F112N is a through-hole part. The supplier device package is 16-PDIP, which fits standard 0.100-inch pitch breadboards and prototyping boards — a common choice for lab builds and legacy designs.