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Texas Instruments SN74F109D — Discrete Semiconductors

SN74F109D Texas Instruments JK Flip-Flop, 150 MHz, 16-SOIC

MPNSN74F109D
End of Life

Texas Instruments 74F series JK flip-flop, SN74F109D, dual 1-bit, positive-edge triggered, complementary outputs, set and reset, 150 MHz clock, 8ns propagation delay, 16-SOIC surface mount.

$0.95Ref. price · indicative, final on quote
Texas Instruments SN74F109D datasheet (PDF)
Packaging16-SOIC (0.154", 3.90mm Width)
RoHSROHS3 Compliant
Series74F
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74F109D specifications
ParameterValue
TypeJK Type
Series74F
Output typeComplementary
Trigger typePositive Edge
MountingSurface Mount
Supply voltage4.5V ~ 5.5V
Current - quiescent17 mA
Current - output high, low1mA, 20mA
Clock frequency150 MHz
Operating temperature0°C ~ 70°C (TA)
PackageTube
FunctionSet(Preset) and Reset
Case16-SOIC (0.154\", 3.90mm Width)
Number of elements2
Number of bits per element1
Max propagation delay @ v, max CL8ns @ 5V, 50pF

Product details

Active 74F JK flip-flop for 5V synchronous logic

The SN74F109D: The 8 ns maximum propagation delay at 5 V and 50 pF load defines the timing budget for the 74F bus — the output settles within one 125 MHz clock period, leaving margin for setup and hold at the receiving flip-flop.

Quiescent current is 17 mA typical across the supply range, and the outputs can source 1 mA or sink 20 mA — enough to drive one or two standard TTL loads or a 74F input without external buffers. The ROHS3 compliance confirms no restricted substances in the package or lead finish.

Sourcing posture for BOM planning

Texas Instruments lists the SN74F109D as an active product. No pin-compatible second-source is listed in the manufacturer's cross-reference data.

Frequently asked questions

What is the SN74F109D's clock frequency and propagation delay?

The maximum clock frequency is 150 MHz. The maximum propagation delay is 8 ns at 5 V supply and 50 pF load, which sets the timing margin for synchronous designs operating at 125 MHz or below.