Single-gate inverter for sub-2.7V rails
It takes one input and delivers a complementary output, packaged in a 5-pin SC-70-5 (SOT-353) footprint. Key specs: quiescent current maxes at 10 µA, output drive is 9 mA source and 9 mA sink, and propagation delay hits 1.9 ns at 2.5V with a 30 pF load.
Where the 0.8V floor matters
The 0.8V minimum supply is what separates the 74AUC family from older 74LVC or 74AHC parts that stop at 1.65V or 2V. If your design has a 1.0V or 1.2V core rail — common in modern MCUs, FPGAs, and DDR memory interfaces — this inverter runs directly off that rail without an extra regulator. The 1.9 ns propagation delay at 2.5V is fast enough for most glue-logic paths, but at 0.8V expect the delay to increase; the datasheet's 1.9 ns figure is specified at 2.5V with 30 pF load. Input logic levels are defined: low is 0V to 0.7V, high is 1.7V minimum. That 1.7V high threshold means a 1.8V logic output drives it cleanly, but a 1.2V output may not — check the VOH of the driving device against the 1.7V VIH spec.