Octal buffer for mixed-voltage buses
The 3-state outputs let you share a data bus across multiple peripherals — pull the output-enable pins high to float the bus during power sequencing or when another device drives the line.
The 1.65 V minimum supply lets it work directly with a 1.8 V FPGA or SoC bank, while the 3.6 V maximum keeps it safe on a nominal 3.3 V rail with a 5% tolerance. No extended-temperature or automotive-grade variant here — if you need -40°C to 125°C or AEC-Q100, look at the 74LVC or 74AVCH families in similar pinouts.
TI lists this part as Active, so it remains in regular production with no announced end-of-life. The ROHS3 compliance covers all current EU substance restrictions, including the four phthalates — no special handling or exemption paperwork needed for lead-free reflow. The 20-SOIC wide-body package is a common footprint, stocked by multiple distributors; no single-source risk on this one.
Surface-mount 20-SOIC with 0.295-inch (7.50 mm) body width — the wide SOIC, not the narrow 3.9 mm version. The supplier device package is 20-SOIC. Standard MSL 1 for this package type, so no bake-out required before reflow as long as the bag seal is intact.