74ALVC triple NAND — 3ns at 3.3V
The SN74ALVC10D is a triple 3-input NAND gate from TI's 74ALVC family, operating from 1.65V to 3.6V. Its 3ns max propagation delay at 3.3V with a 50pF load makes it a fit for high-speed logic paths where the 74LVC sibling's 4.7ns would eat into timing margin. Three independent NAND gates per package, each with three inputs — useful for decode logic, gated clock trees, or enable circuits where you need the AND-NOT function in a single gate delay.
14-SOIC — rework-friendly footprint
14-SOIC body, 3.90mm width, 1.27mm pin pitch. The 0.154-inch wide SOIC is a standard footprint that reflows cleanly with a hot-air station — pin 1 is clearly marked by the chamfer on the package body, so orientation is unambiguous under a loupe. Supplied in tube — not tape-and-reel. If your pick-and-place feeder expects tape, factor in a tube-to-tape transfer step, or order the tape-and-reel variant if one exists in the family.
Supply and drive — 24mA output, 10µA idle
Outputs source and sink 24mA each, enough to drive a standard CMOS load or a short trace without a buffer. Quiescent current sits at 10µA max — negligible in battery-powered designs where the gate sits idle most of the time. Input logic thresholds are 0.7-0.8V for low and 1.7-2.0V for high across the supply range — compatible with 1.8V and 2.5V logic families without external level translation.
The 74ALVC series is a mature logic family; TI continues to manufacture these alongside the newer AUP and LVC families.