8-bit transparent latch for bus-oriented data paths
The SN74ALS573CDW is an 8-bit D-type transparent latch from TI's 74ALS family, designed for buffered data storage on a microprocessor bus or memory interface. With tri-state outputs and a 2ns propagation delay, it handles address latching and data demultiplexing in 5V systems where the bus must float during inactive cycles.
Delay and drive — what the numbers mean for bus timing
The 2ns propagation delay is the time from the latch-enable edge to valid data at the output — in a 10 MHz bus cycle (100 ns period), this leaves 98 ns for setup and hold at the receiving device, so the latch itself is rarely the timing bottleneck. The output drive is asymmetric: 2.6 mA source, 24 mA sink. The 24 mA sink current handles standard TTL loads and drives the bus capacitance on the falling edge; the 2.6 mA source is lighter, so the rising edge into a heavily loaded bus may need an external pull-up if the rise time must stay under a few nanoseconds.
The commercial temperature grade (0 °C to 70 °C) limits it to indoor, conditioned environments — not suitable for automotive or outdoor enclosures without active thermal management.