14 ns propagation delay — timing closure for 5 V bus logic
The SN74ALS32DR is a quad 2-input OR gate from TI's 74ALS family, packing four independent gates into a 14-SOIC footprint. The 14 ns max propagation delay at 5 V into a 50 pF load sets the timing budget for address decoding, control signal gating, or interrupt combining on a 5 V backplane — at 5 V, the ALS series runs faster than the original 74LS but draws less power than the 74F, a middle ground for bus-oriented designs where edge rate matters but supply current is constrained.
Output drive and fan-out budget
Each gate sources 400 µA and sinks 8 mA at the output — the sink current drives up to 10 standard 74ALS loads (0.8 mA per input), while the source side is limited to a single ALS load. For fan-out beyond one gate, buffer the output or use the 74F series which delivers 1 mA source at similar speeds.
Supply rail and temperature grade
Input thresholds are TTL-compatible: 0.8 V low, 2 V high.
Package and board integration
The SOIC package is rework-friendly with a hot-air pencil; no thermal pad or exposed paddle to manage.