Dual JK flip-flop in the 74ALS family
The SN74ALS112ANSR is a dual 1-bit JK flip-flop from Texas Instruments' 74ALS logic family, with Set (Preset) and Reset inputs and complementary outputs. It triggers on the negative edge of the clock, making it suitable for synchronous counter and register applications where the falling edge defines the state transition.
Timing and drive margins for the BOM
Maximum clock frequency is 30 MHz, which sets the upper limit for synchronous operation in the target system. Output drive capability is 400 µA sink/source on the high side and 8 mA on the low side, sufficient for driving standard TTL loads but not high-fanout buses without buffering. Quiescent current draw is 4.5 mA typical, a consideration for power budgets in systems where the flip-flop bank is always clocked.
Supplied in a 16-pin SOIC package with a body width of 5.30 mm (0.209"), the SN74ALS112ANSR is a surface-mount device that mounts on a standard SOIC-16 footprint. The tape-and-reel packaging option supports automated pick-and-place assembly for volume production.