8-bit transparent latch with tri-state bus hold
The SN74AHCT373DW: The latch is transparent when the latch-enable (LE) input is high; when LE goes low, the data is latched. Output-enable (OE) control puts the outputs in a high-impedance state for bus sharing. Propagation delay is rated at 1ns, which is fast enough for most address/data bus applications in industrial control, telecom, and test equipment. The 8mA output current per channel is adequate for driving CMOS logic inputs but won't directly drive LEDs or relays without a buffer stage. For wider-temperature needs, check the AHCT family's automotive-grade variants.
Package and footprint — 20-SOIC wide body
Supplier device package is 20-SOIC. The wide-body SOIC uses a 1.27mm pin pitch — standard for this form factor.
Single-supply 5V logic — compatibility check
The SN74AHCT373DW is a single-supply device with a single independent latch circuit. The 4.5V to 5.5V range means it runs on a nominal 5V rail — do not feed it 3.3V directly. Input thresholds are TTL-compatible, so it can interface with 3.3V logic if the 3.3V output high is above the VIH(min) of 2.0V typical for AHCT. For bidirectional 5V/3.3V buses, add a level shifter or use the AHC family with wider supply tolerance.