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Texas Instruments SN74AHC132PW — Logic ICs

SN74AHC132PW – 74AHC Quad 2-Input NAND Gate with

MPNSN74AHC132PW
End of Life

Texas Instruments 74AHC series, SN74AHC132PW, Quad 2-Input NAND Gate with Schmitt-Trigger Inputs, 2V to 5.5V supply, 8mA output drive, 9.7ns max delay @5V/50pF, -40°C to 85°C, 14-TSSOP package.

$1.16Ref. price · indicative, final on quote
Packaging14-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Series74AHC
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74AHC132PW specifications
ParameterValue
Series74AHC
Logic typeNAND Gate
MountingSurface Mount
Voltage2V ~ 5.5V
Current - quiescent2 µA
Current - output high, low8mA, 8mA
I/O channels2
Operating temperature-40°C ~ 85°C
PackageTube
FeaturesSchmitt Trigger
Case14-TSSOP (0.173\", 4.40mm Width)
Number of circuits4
Input logic level - low0.9V ~ 1.65V
Input logic level - high2.2V ~ 3.85V
Max propagation delay @ v, max CL9.7ns @ 5V, 50pF

Product details

The SN74AHC132PW is a Texas Instruments 74AHC-series quad 2-input NAND gate with Schmitt-trigger inputs, packaged in a 14-TSSOP (4.40 mm width) for surface-mount assembly. It operates across a 2V to 5.5V supply range, making it compatible with 3.3V and 5V logic domains.

9.7 ns propagation delay – timing budget for cascaded gates

Maximum propagation delay is 9.7 ns at 5V with a 50 pF load. At lower supply voltages (3.3V or 2.5V) the delay increases – budget extra margin when chaining multiple gates in a critical path. The 8 mA symmetrical output drive (both high and low) is sufficient for driving a few CMOS inputs or a short PCB trace; for heavier loads (LEDs, relays) add a buffer or transistor stage.

2 µA quiescent current – low static power for always-on blocks

Quiescent current is a maximum of 2 µA across the supply range, so the gate adds negligible static draw to battery-powered or energy-harvesting designs. The input logic levels (low: 0.9V to 1.65V; high: 2.2V to 3.85V at 5V) are TTL-compatible, easing mixed-voltage interface design.

Active lifecycle – no near-term EOL risk

Frequently asked questions

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