Quad 2-input OR gate in 5 V logic
The SN74ACT32PW is a Texas Instruments quad 2-input OR gate from the 74ACT family, packaged in a 14-TSSOP (4.40 mm width) for surface-mount assembly. It performs the OR logic function on four independent 2-input gates, each capable of sinking or sourcing 24 mA — enough to drive multiple CMOS inputs or a single TTL load without a buffer. Input thresholds are TTL-compatible: 0.8 V low, 2 V high, so it interfaces directly with legacy 5 V TTL outputs or 3.3 V logic through a level translator.
Timing and drive — what 9 ns and 24 mA mean for the bus
Maximum propagation delay is 9 ns at 5 V with a 50 pF load. In a 5 V synchronous bus clocked at 50 MHz (20 ns period), 9 ns leaves 11 ns for setup and hold — tight but workable if the trace lengths are matched. For slower buses (10-20 MHz), the margin is comfortable. The 24 mA symmetric output drive (both high and low) means the gate can fan out to about 10 standard LS TTL loads or 50 CMOS loads at 5 V. If the downstream inputs are all CMOS, the actual load is capacitive — the 9 ns delay already includes 50 pF, so adding more capacitance stretches the edge and eats timing margin. Quiescent current is 2 µA max — essentially leakage. In a battery-powered system running at 5 V, the gate itself draws negligible power; the dynamic current scales with switching frequency and load capacitance per the standard CMOS formula.
Temperature range and compliance
The 14-TSSOP package has a typical junction-to-ambient thermal resistance around 150°C/W; at 24 mA output into a 50 pF load switching at 10 MHz, the self-heating is under 10°C above ambient. Lifecycle status is active per Texas Instruments, with ROHS3 compliance.