With a maximum propagation delay of 9 ns at 5 V and 50 pF load, this gate keeps combinatorial delays tight enough for 20–30 MHz clocked buses without adding a full clock cycle of skew. The 0.8 V low-level and 2 V high-level input thresholds are TTL-compatible, so it directly interfaces with older 5 V logic families like LS and HCT without level translation.
The 14-DIP through-hole package is a mature, widely stocked form factor, so supply continuity is straightforward through independent distribution channels.