8-bit D-type flip-flop with inverted bus drive
The SN74AC564DBLE: The 95 MHz maximum clock frequency and 10.5 ns propagation delay (at 5 V, 50 pF load) mean it keeps up with moderate-speed buses without adding a full clock cycle of latency — the output settles well within a 10.5 ns window after the clock edge, so downstream logic sees a stable inverted value by the next clock edge.
The supplier device package is also 20-SSOP, so the footprint matches the package/case — no second-guessing the land pattern.
RoHS flag — check your BOM compliance
Texas Instruments lists this part as RoHS non-compliant — if your assembly line or end-product requires RoHS exemption-free compliance, this part will not pass a standard RoHS inspection without a waiver or an alternative finish.