7400-series NOR gate in a 14-pin DIP
The Texas Instruments SN7425N is a 7400-series NOR gate with two independent circuits, each providing four inputs. Housed in a 14-pin DIP (0.300", 7.62mm) with through-hole mounting, the SN7425N suits legacy designs, breadboard prototyping, or any board where a DIP footprint is already established.
Timing and drive — what the numbers mean for the board
Maximum propagation delay is 22 ns at 5 V with a 15 pF load — this sets the data-rate ceiling for a single gate in a 5 V logic chain. The delay adds across cascaded stages, so a four-gate path sees roughly 88 ns of total propagation delay before the output settles. Output drive is asymmetric: 800 µA sourcing (logic-high) and 16 mA sinking (logic-low). The low-side drive is adequate for driving a standard TTL fan-out of ten loads, but the high-side current limits direct LED or relay drive — a pull-up resistor or buffer stage is needed for loads above 800 µA. Input logic thresholds are 0.8 V (low) and 2 V (high) — compatible with 5 V TTL and CMOS families that meet the same levels. The strobe feature (pin 1 on each gate) allows the output to be forced high regardless of the input state, useful for bus isolation or test-mode gating.
Sourcing and compliance — active lifecycle, no obsolescence risk
For BOM planning, the active lifecycle means no forced redesign or qualification effort is needed to keep the line running.