The Texas Instruments SN65LVDS96DGGRG4 is a 3-to-21 LVDS deserializer that takes three differential LVDS input pairs and expands them into 21 single-ended LVTTL output lines. It handles an aggregate data rate of 1.428 Gbps, which works out to 476 Mbps per differential pair. You will find it in the 48-pin TSSOP package — the same footprint as the standard 48-TFSOP, 6.10 mm body width.
1.428 Gbps data rate — what it buys the video link
The 1.428 Gbps aggregate data rate is the number that decides whether this part clears the video bandwidth budget. For a typical 24-bit color display at 60 Hz with blanking overhead, that rate supports resolutions up to around WUXGA (1920 x 1200) without compression. The three LVDS input pairs carry the pixel data, syncs, and clock embedded in the stream, and the 21 LVTTL outputs present the parallel bus to the timing controller or FPGA. If the target panel needs more than 21 parallel lines or a higher pixel clock, you are looking at a wider deserializer or a dual-device configuration.
Industrial temperature range — where it survives
The commercial-grade 0°C to 70°C sibling would not survive the same duty cycle. No derating curve to manage at the top end — the 85°C limit is the operating ceiling, not a storage number.
That means TI is still manufacturing it, no last-time-buy notice has been issued, and the supply channel is the standard distribution network — not surplus or broker stock.
The DGGRG4 suffix tells you two things: the package is a 48-pin TSSOP (the G suffix), and it ships on Tape & Reel (the R and G4 indicators). The 48-TSSOP footprint is 6.10 mm wide, 0.5 mm pitch — a common land pattern shared with other 48-pin TSSOP deserializers and serializers in the same family.