The Texas Instruments SN65LVDS96DGGR is a 3-input, 21-output LVDS deserializer that converts three serial LVDS data streams into a single 21-bit wide LVTTL parallel bus. It accepts serial data at an aggregate rate of 1.428 Gbps, which supports high-resolution video links — think 24-bit color plus control signals over a twisted-pair cable at WUXGA or 1080p60 rates. The LVDS inputs are differential and terminated on-die, so the external termination resistor count drops. The 21 LVTTL outputs clock out on a single rising edge of the pixel clock, simplifying the FPGA or ASIC capture logic. Typical applications include flat-panel display interfaces, projector engines, and any system where a wide parallel bus must be serialized across a cable or backplane to save pins and reduce EMI.
The 1.428 Gbps figure is the sum of all three LVDS channels. Each channel runs at 476 Mbps, which is fast enough to carry 24-bit RGB data at 60 Hz with 720p or WXGA resolutions without compression. For 1080p60 you'll need to check the pixel clock against the deserializer's output clock rate — the part can handle up to 112 MHz on the parallel bus (derived from the serial rate divided by 7). The LVDS input threshold is tight (100 mV differential typical), so a clean signal at the receiver with at least 200 mV swing after cable loss keeps the bit-error rate low. If your cable run exceeds 5 meters, budget a pre-emphasis or equalizer at the serializer side.
Package and supply — layout constraints at this speed
The 48-TFSOP (0.240", 6.10 mm width) / 48-TSSOP footprint is a common fine-pitch SOIC derivative — 0.5 mm lead pitch, so a 4-layer board with a solid ground plane under the part is recommended. The LVDS inputs are 100 Ω differential and self-biased, so no external bias resistors are needed. The LVTTL outputs drive 5 pF loads cleanly — if you're driving a long parallel bus, add series damping resistors (22 Ω to 33 Ω) near the outputs to suppress reflections.
Temperature grade and industrial qualification
The industrial range covers most factory-floor and surveillance-camera environments. At the cold end, the PLL lock time may stretch — allow a 10 ms startup delay after power-up before sending serial data.
For a BOM line this is a low-risk pick — no last-time-buy scramble, no second-source hunt required for continuity.