400 Mbps per channel — signal-integrity budget
Each of the two drivers handles 400 Mbps, which corresponds to a 200 MHz clock rate for DDR-style data or 400 MHz for single-edge clocking. At that speed, the 3.3 V LVDS swing (~350 mV differential) keeps EMI low, but the PCB trace impedance needs to be held to 100 Ω differential ±10% to avoid reflections that close the eye. The driver's output edge rates are fast enough that stub lengths on the transmission line should be kept under 0.5 inches — a common layout discipline for this data rate.
The base product number 65LVDS9638 covers the family, and the DG4 suffix denotes the RoHS-compliant, lead-free finish in the 8-SOIC package.