Dual LVDS receiver in a compact SOIC-8
With a 150 Mbps data rate per receiver, this part comfortably handles 100Base-TX (125 Mbps) or parallel LVDS links running at 75 MHz DDR. The dual-channel configuration means two independent LVDS lines terminate in one package, saving board area versus two single receivers. The 3.3 V nominal supply aligns with common FPGA and ASIC I/O banks, so no level translation is needed on the receive side.