The 150 Mbps per-channel ceiling sets the maximum serial bit rate the receiver can recover with adequate eye margin. For a 100 MHz pixel clock in a flat-panel display link or a 125 MHz serialized data stream from a high-speed ADC, this part works. Above that, the internal comparator and differential amp lose enough setup/hold margin that bit-error rate climbs. If your link runs at 200 Mbps or higher, step up to a 400 Mbps-rated LVDS receiver in the same 8-SOIC footprint — the pinout is usually compatible, but verify the supply current bump.
Receiver-only — no bus drive capability
With 0 drivers and 2 receivers on-chip, this part terminates and decodes LVDS differential pairs but cannot generate the differential swing itself. That means the far end of the cable needs a separate LVDS driver (e.g., SN65LVDS9637D or SN65LVDT31). A common mistake is ordering this receiver when the BOM actually calls for a transceiver — check the driver count field on your line item before committing.