Dual LVDS receiver — 150 Mbps, 3.3 V supply, active production
150 Mbps — what the data rate tells you
The 150 Mbps per-channel rating is the maximum serial bit rate the receiver can maintain with adequate eye margin. For a 75 MHz clock or a 150 Mbps data stream, the propagation delay and skew between the two channels must fit within the timing budget of the receiving FPGA or ASIC. At lower rates (25–100 Mbps) the part runs with more noise margin; at the ceiling, keep trace lengths matched and unterminated stubs short. The part is a receiver only — it expects an LVDS driver on the other end of the differential pair.
Supply rail and decoupling
A 100 nF ceramic cap at each supply pin, placed within 2 mm of the pin, plus a 1 µF bulk cap per device, keeps the supply noise below the receiver's common-mode rejection threshold.