Dual LVDS receiver in a small exposed-pad package
It handles a data rate up to 150 Mbps per channel, making it suitable for high-speed point-to-point links in industrial backplanes, camera interfaces, and display interconnects where noise immunity over twisted-pair or PCB traces matters.
150 Mbps — what the data rate means for the link
At 150 Mbps the receiver supports LVDS signalling with a typical differential threshold of 100 mV, giving good noise margin on cables up to a few metres. The 150 Mbps rate is the per-channel maximum; the two receivers operate independently, so a single IC can terminate two separate differential pairs. For a 24-bit RGB video link at 60 Hz with a 25 MHz pixel clock, this part handles the parallel data lines without needing a deserialiser.
Supply and logic compatibility
No level translation is needed between the receiver output and a 3.3V FPGA bank or microcontroller GPIO. The input common-mode range follows the LVDS standard of 0 V to 2.4 V with a 100 mV differential swing.
Package and footprint note
The SN65LVDS9637DGN comes in an 8-HVSSOP package (3.00 mm width, exposed thermal pad) for surface-mount assembly. The package is MSL 1 per the 65LVDS family, so no bake is required before reflow if the dry-pack seal is intact.