The SN65LVDS9637D converts a differential LVDS signal pair into a single-ended CMOS output, handling data rates up to 150 Mbps per channel.
At 150 Mbps the receiver can handle a 75 MHz clock or a 150 Mbps NRZ data stream with adequate setup-and-hold margin for most FPGA and ASIC inputs. The differential input threshold is LVDS-standard (typically ±100 mV), so the part works directly with any LVDS driver that meets the TIA/EIA-644 specification. If your link runs at lower rates — say 10 to 100 Mbps — the margin only improves; no speed-grade derating is needed.
Supply rail and temperature — production-fit checks
If your board uses a 3.0V rail, verify the regulator output stays above 3.0V under load.