LVDS deserializer, 1.904 Gbps aggregate
The SN65LVDS94DGGR is a Texas Instruments LVDS deserializer that takes four serial LVDS data streams and converts them to 28 parallel LVTTL outputs. The aggregate data rate of 1.904 Gbps means each of the four LVDS pairs carries up to 476 Mbps, enough for a 24-bit RGB video signal plus control data over a single differential pair cable. The 4:28 channel ratio matches the common flat-panel display interface where a source (GPU, FPGA, or serializer) sends pixel data over four differential pairs and the deserializer recovers the parallel bus on the display side. The LVTTL output levels at 3.3 V nominal interface directly with most TFT timing controllers without external level shifting.
The reel quantity is typically 2000 pieces per reel for the 56-TSSOP package, though the exact count is confirmed at quote.