1.904 Gbps deserialiser for flat-panel display links
The Texas Instruments SN65LVDS94DGG is an LVDS deserialiser that takes four LVDS data pairs and a clock pair from a serialiser and reconstructs 28 parallel LVTTL outputs plus a pixel clock. The aggregate serial data rate of 1.904 Gbps supports display resolutions up to UXGA (1600×1200) at 60 Hz with 18-bit colour depth over a single differential pair cable.
LVDS input margin and layout considerations
The four LVDS inputs accept a differential swing of 100 mV to 450 mV with a common-mode range of 0.85 V to 1.575 V, which is the standard TIA/EIA-644 LVDS level. On a 56-TSSOP package (6.10 mm body width), the differential pairs should be routed with 100 Ω controlled impedance and kept matched in length to within 5 mm to avoid skew-induced jitter at 1.904 Gbps aggregate. The 28 LVTTL outputs drive 3.3 V CMOS levels with 24 mA sink/source capability, enough to fan out to the panel timing controller without external buffers on short PCB traces.
TI has not issued a last-time-buy notice or end-of-life notification for this base part number.