SN65LVDS93ADGGR

Texas Instruments

Texas Instruments SN65LVDS93ADGGR LVDS serializer, 3.78 Gbps aggregate data rate, 28 LVTTL inputs, 4 LVDS outputs, 3V–3.6V supply, 56-TSSOP, -40°C to 85°C.

SN65LVDS93ADGGR
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[IN STOCK] In Stock: 142 pcs
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MOQ 1 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

SN65LVDS93ADGGR specifications
Parameter / AttributeSpecification / Value
Input typeLVTTL
Output typeLVDS
MountingSurface Mount
Supply voltage3V ~ 3.6V
I/O channels28
Operating temperature-40°C~85°C(TA)
PackageTape & Reel (TR); Cut Tape (CT)
FunctionSerializer
Data rate3.78Gbps
Case56-TFSOP (0.240\", 6.10mm Width)

Technical details

28-to-4 LVDS serializer for display and video links

The Texas Instruments SN65LVDS93ADGGR is a 28-channel LVTTL-input to 4-channel LVDS-output serializer designed for high-speed parallel-to-serial conversion in display interfaces and video data links. It aggregates 28 bits of parallel data at rates up to 3.78 Gbps aggregate, reducing a wide parallel bus to a slim 4-pair LVDS cable or PCB trace.

3.78 Gbps aggregate — sizing the display link bandwidth

The 3.78 Gbps aggregate data rate is the sum of all four LVDS output pairs running simultaneously. For a typical 24-bit color display with 24 data bits plus 4 control/hsync/vsync signals, each LVDS pair carries about 945 Mbps, which supports resolutions up to WUXGA (1920x1200) at 60 Hz with reduced blanking. The 28 inputs accept LVTTL levels, so the parallel side interfaces directly with a graphics controller or FPGA I/O bank running at 3.3V. On the serial side, the four LVDS outputs drive standard 100-ohm differential pairs, and the differential swing is compliant with TIA/EIA-644 LVDS.

Supply and temperature — staying inside the operating window

The part is not rated for 5V input signals on the LVTTL side — exceeding the supply rail on any input pin violates the absolute-maximum ratings. The 56-TSSOP package (6.10 mm body width) is a fine-pitch surface-mount footprint that requires careful PCB layout for signal integrity on the LVDS pairs.

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