Eight LVDS receivers in a 38-TSSOP — what you're getting
The Texas Instruments SN65LVDS388DBT is an eight-channel LVDS receiver in a 38-TSSOP package. It takes in LVDS differential signals on eight lines and outputs single-ended CMOS levels — exactly what you need when a parallel bus or a set of clock/data pairs arrives over a twisted-pair cable and you want to land them on a 3.3 V FPGA or ASIC bank.
Obsolete — the sourcing reality
For a new design, look at TI's active LVDS receiver family (e.g., SN65LVDS32 series) and verify footprint and electrical compatibility.
Package and footprint — what to check
That's a fine-pitch, surface-mount package with a 0.5 mm lead pitch typical of TSSOP. The narrow body width means the PCB footprint is compact, but the pad spacing demands a decent solder mask and a controlled reflow profile. No exposed thermal pad on this package, so thermal dissipation is through the leads only — keep the ambient airflow reasonable if all eight channels are running at full data rate.