Eight LVDS receivers in a single 38-TSSOP
The Texas Instruments SN65LVDS388ADBTR is an eight-channel LVDS receiver in the 65LVDS family, designed to convert low-voltage differential signaling (LVDS) back to single-ended CMOS levels. It handles a per-channel serial data rate up to 200 Mbps, making it a fit for high-speed backplane, cable, or clock distribution links where eight differential pairs need to be received on a single IC.
200 Mbps per channel — what the eye diagram needs
At 200 Mbps the bit period is 5 ns. For a backplane trace longer than a few inches, the differential skew and common-mode rejection of this receiver become the limiting factors, not the raw data rate. The LVDS standard's 350 mV typical swing keeps EMI low, but the termination resistor (100 Ω across the pair at the receiver input) must be placed within 0.5 inch of the pins to avoid reflections that close the eye. If your system runs at 150 Mbps or below, you gain margin on setup-and-hold timing at the FPGA or ASIC input.
That means no announced end-of-life, no last-time-buy window to track. The part is ROHS3 compliant. The base product number 65LVDS388 covers the family; the DBTR suffix identifies the 38-TSSOP tape-and-reel variant.
Supply rail and termination checklist
The 38-TFSOP package, also called 38-TSSOP, has a 4.40 mm body width and 0.5 mm pin pitch — a standard footprint that many assembly houses can handle with a fine-pitch stencil.