That is a dense, single-device solution for parallel data buses — think camera links, FPGA-to-FPGA chip-to-chip links, or high-speed backplanes where every square millimeter counts.
TI lists the SN65LVDS387DGGR as Active. That means no end-of-life notice, no last-time-buy scramble, and no forced redesign for the foreseeable future. For a BOM line that feeds a multi-year production run, this part does not introduce supply-chain risk from the manufacturer side.
630 Mbps per pair — sizing the signal-integrity budget
Each of the 16 drivers switches at up to 630 Mbps. At that edge rate, PCB layout matters: controlled impedance (typically 100 Ω differential), short stubs, and proper termination at the receiver end.
Tape & Reel — ready for the pick-and-place line
No tube-to-reel transfer step needed at the kitting stage. The 64-TSSOP body (6.10 mm width) is a common footprint; MSL level should be confirmed from the latest TI packing label before reflow, but the package style is well-established in production.