Texas Instruments SN65LVDS34DRG4, LVDS dual receiver, 400 Mbps data rate, 50 mV hysteresis, 3V to 3.6V supply, 8-SOIC package, -40°C to 85°C, active.
| Parameter | Value |
|---|---|
| Type | Receiver |
| Mounting | Surface Mount |
| Supply voltage | 3V ~ 3.6V |
| Protocol | LVDS |
| Operating temperature | -40°C ~ 85°C |
| Package | Tape & Reel (TR) |
| Data rate | 400Mbps |
| Case | 8-SOIC (0.154\", 3.90mm Width) |
| Receiver hysteresis | 50 mV |
| Number of drivers (Receivers) | 0/2 |
The 400 Mbps data rate covers most LVDS clock and data links up to short-reach serial video or gigabit Ethernet PHY interfaces. The 50 mV hysteresis is the key differentiator from a plain comparator — it prevents output chatter when the differential input sits near the threshold, which matters on cables or backplane traces with reflections. Supply tolerance is tight (3V to 3.6V); a 3.3V rail with ±5% regulation keeps the receiver inside its window.
No NRND or LTB notices are on file.
The SN65LVDS34DRG4 supports a maximum data rate of 400 Mbps per channel, sufficient for LVDS clock distribution, serial video links, and high-speed control interfaces.