Dual LVDS receiver with 50 mV hysteresis
Standard SOIC footprint, no assembly surprises
Housed in an 8-pin SOIC (3.90 mm width) with surface-mount termination, the SN65LVDS34DR uses a common footprint that aligns with standard reflow profiles. No thermal pad or exposed paddle — junction-to-ambient thermal management is straightforward for the typical 400 Mbps signaling load.