At 560 Mbps each of the four receivers can clock a parallel LVDS bus without multiplexing, which simplifies the FPGA or ASIC interface on the receiving end. The 50 mV hysteresis is a deliberate margin adder: it prevents the output from chattering when the differential input sits near the threshold, a common failure mode on long backplane traces or through connectors with intermittent contact. If your system runs at lower rates (100–200 Mbps), the hysteresis still helps — it does not degrade with slower edges.
SN65LVDS349PW LVDS Receiver, 560 Mbps, 16-TSSOP
MPNSN65LVDS349PW
Active
Texas Instruments 65LVDS series, SN65LVDS349PW, LVDS Receiver, 560Mbps, 0/4 Drivers/Receivers, 3V ~ 3.6V, -40°C~85°C, Surface Mount, 16-TSSOP.
$11.9900Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026
Specifications
| Parameter | Value |
|---|---|
| Type | Receiver |
| Series | 65LVDS |
| Mounting | Surface Mount |
| Supply voltage | 3V ~ 3.6V |
| Protocol | LVDS |
| Operating temperature | -40°C~85°C |
| Package | Tube |
| Data rate | 560Mbps |
| Case | 16-TSSOP (0.173\", 4.40mm Width) |
| Receiver hysteresis | 50 mV |
| Number of drivers (Receivers) | 0/4 |
Product details
Frequently asked questions
What is the data rate of SN65LVDS349PW?
The SN65LVDS349PW supports a data rate of 560 Mbps per channel.