Four-channel LVDS receiver for high-speed backplane links
Typical applications include clock distribution, backplane data links, and high-speed serial interfaces in telecom, industrial control, and test equipment where low noise and low power are priorities.
Each of the four receivers handles a 560 Mbps LVDS input stream. That rate covers 28:1 deserialised data at 20 MHz or a direct 560 MHz clock distribution. The 50 mV of built-in receiver hysteresis provides noise margin on idle or lightly-loaded buses without external fail-safe resistors — one less component per channel on the BOM. The LVDS common-mode range of 0 V to 2.4 V (typical for the 65LVDS family) mates directly to standard LVDS drivers over twisted-pair or differential PCB traces up to several metres.