Quad LVDS receiver for backplane and cable links
It converts differential LVDS signals at rates up to 400 Mbps per channel into single-ended CMOS outputs, with 50 mV of built-in hysteresis to reject noise on long traces or twisted-pair cables.
Each of the four receivers handles a 400 Mbps serial stream, which is the practical ceiling for most LVDS point-to-point links inside a chassis or between boards. At that rate the 50 mV hysteresis is the spec that matters more than the raw bit count — it gives you about 25 mV of noise margin above the 100 mV minimum differential threshold, which cleans up the eye on a 3-meter cable or a backplane with a few connectors. If your link runs at 200 Mbps or slower, the margin only improves.