Quad LVDS receiver — 400 Mbps with 50 mV hysteresis
The Texas Instruments SN65LVDS3486DG4 is a quad-channel LVDS receiver in the 65LVDS family, designed to convert differential LVDS signals to single-ended 3.3V CMOS logic levels.
The 400 Mbps per-channel data rate supports common LVDS applications such as clock distribution, high-speed serial backplanes, and video data links. At this rate, the receiver can handle 200 MHz clock signals or 400 Mbps NRZ data with adequate setup-and-hold margin. The 50 mV hysteresis is a practical advantage: it prevents output chatter when the differential input signal is slow-moving or sits near the threshold, which is typical in systems with long cables or daisy-chained receivers.
For designs that must survive cold starts or high ambient heat, this grade provides the necessary margin.
The SN65LVDS3486DG4 is supplied in a 16-pin SOIC package with a body width of 0.154 inches (3.90 mm), which is the narrow-body SOIC-16 footprint. This is distinct from the wider 0.300-inch SOIC-16; verify the PCB land pattern before layout. The package is surface-mount and ships in tube form.