Quad LVDS receiver for point-to-point and multidrop links
The Texas Instruments SN65LVDS33PWR is a quad-channel LVDS receiver in a 16-TSSOP package. It converts four differential LVDS signal pairs into four single-ended CMOS outputs, with a guaranteed data rate of 400 Mbps per channel. The 50 mV of built-in receiver hysteresis provides noise rejection on long backplane traces or cable runs where common-mode shifts are a concern.
400 Mbps per channel — signal integrity budget
At 400 Mbps the receiver handles 200 MHz clock frequencies or 400 Mbps NRZ data. The 50 mV hysteresis means the input threshold has a dead zone that rejects differential noise below that level, which is useful when the LVDS pair shares a cable bundle with switching power lines or motor phases. The receiver inputs present a standard 100 Ω differential termination load (external resistor required — not on-die), so the line impedance matching is a board-level decision. For a 400 Mbps link, keep the stub length under 0.5 inches and place the termination resistor within 0.1 inches of the receiver input pins.
The ROHS3 compliance covers current EU and global solderability requirements, so no exemption expiry to track.