Quad LVDS receiver for 400 Mbps serial links
The Texas Instruments SN65LVDS33DR is a quad-channel LVDS receiver designed for high-speed differential signaling at 400 Mbps per channel. It accepts low-voltage differential signals and converts them to 3.3 V CMOS levels, with 50 mV of built-in hysteresis to reject noise on long backplane traces or cables.
For a production BOM this removes the supply-risk flag that obsolete or NRND parts carry.
No special baking or handling beyond MSL 1/2/3 typical for SOIC—check the reel label for the specific moisture sensitivity level.
40 µA typical quiescent – power budget note
For a backplane with all four channels active at full rate, budget around 25 mA typical per the family datasheet (not shown in this brief listing). The 50 mV hysteresis helps maintain clean edges on lossy FR-4 traces without external termination tweaks.