Texas Instruments 65LVDS series LVDS receiver, SN65LVDS32NSR, quad receiver, 400Mbps data rate, 50 mV hysteresis, 3V–3.6V supply, -40°C to 85°C, 16-SOIC package.
| Parameter | Value |
|---|---|
| Type | Receiver |
| Series | 65LVDS |
| Mounting | Surface Mount |
| Supply voltage | 3V ~ 3.6V |
| Protocol | LVDS |
| Operating temperature | -40°C~85°C |
| Package | Tape & Reel (TR) |
| Data rate | 400Mbps |
| Case | 16-SOIC (0.209\", 5.30mm Width) |
| Receiver hysteresis | 50 mV |
| Number of drivers (Receivers) | 0/4 |
The LVDS input common-mode range (typically 0V to 2.4V) and the 50 mV hysteresis let it reject ground shifts and noise on long cables. Outputs are LVTTL/LVCMOS compatible, so they drive a standard FPGA or ASIC input without level translation.
The 1.27 mm pin pitch is breadboard-friendly with adapter boards. For production, it's a standard SOIC-16 footprint that matches many other quad LVDS receivers, easing second-source qualification.
Both are the same quad LVDS receiver die. The difference is the shipping medium: SN65LVDS32NSR ships in Tape & Reel, while SN65LVDS32DR ships in a different reel or tube configuration. Electrically and pin-for-pin they are identical.