Quad LVDS receiver in a 16-SOIC — what the 400 Mbps and 50 mV hysteresis mean for the link
It handles four independent channels, each rated for 400 Mbps data throughput, making it a fit for high-speed serial links in video interfaces, backplane data transfer, and clock distribution. The 50 mV of on-chip receiver hysteresis helps reject noise on the differential pair, which matters when the cable run extends beyond a few inches or the layout passes near a switching regulator.
Supply rail and temperature grade — what drives the BOM fit
If your board runs a 2.5 V or 1.8 V I/O bank, this receiver needs its own LDO or a separate 3.3 V plane — it will not run from a lower rail.
For dual-sourcing or a drop-in alternate, the SN65LVDS32BD family includes multiple package and temperature variants — the DG4 suffix denotes the 16-SOIC package with lead-free (RoHS) finish.