Quad LVDS receiver for 400 Mbps serial links
The Texas Instruments SN65LVDS32BD is a quad-channel LVDS receiver in a 16-SOIC package. It converts four differential LVDS signal pairs into four single-ended CMOS outputs, supporting a per-channel data rate of 400 Mbps. The 50 mV of built-in receiver hysteresis provides noise margin on long backplane traces or cable runs where common-mode shifts are a concern.
400 Mbps data rate and 50 mV hysteresis — the signal integrity budget
At 400 Mbps the SN65LVDS32BD handles most parallel-to-serial or serial backplane links running at 400 MHz equivalent bit rate. The 50 mV hysteresis is the key spec for noise immunity: it prevents output chatter when the differential input sits near the switching threshold, which happens on idle buses or during cable disconnect. For a 3.3 V LVDS link with 350 mV typical swing, the hysteresis represents about 14% of the signal amplitude — enough to reject coupled noise from adjacent high-speed traces without sacrificing the input threshold window.