What the 1.755 Gbps data rate means for backplane routing
The SN65LVDS314RSKR is a 27-bit LVDS receiver operating at 1.755 Gbps per lane — that is the per-channel signalling ceiling for LVDS on a balanced differential pair. At this edge rate, the trace length between the transmitter and this receiver is limited by the signal rise-time degradation from FR-4 dielectric loss and via stubs; a typical 100-ohm differential pair on a standard PCB will support runs up to roughly 12–18 inches before the eye closes at the receiver input. The part is a pure receiver — no integrated termination or equalisation — so the system designer must place a 100-ohm differential termination resistor within 5 mm of the input pins and account for the receiver's 0.5 V input threshold for a valid differential signal.
The core supply range is 1.65 V to 1.95 V, which maps to a 1.8 V nominal rail with ±8.3 % tolerance — common on FPGA and ASIC boards that share a 1.8 V plane.
RoHS3 compliance covers the full EU substance restriction list including the four phthalates added in EU 2015/863. The package is a 64-VQFN (8x8 mm) with an exposed pad — the lead-frame finish is matte tin, which is compatible with SAC305 solder profiles and does not require a nitrogen reflow atmosphere.