Single LVDS receiver for point-to-point links
The SN65LVDS2DRG4 receiver accepts LVDS-level inputs and provides a single-ended CMOS output.
400 Mbps data rate — signal integrity budget
The 400 Mbps data rate is the key performance spec. At this speed, the receiver handles 200 MHz clock signals or 400 Mbps serial data with a typical input threshold of ±100 mV. The differential input ensures common-mode noise rejection, but the trace pair must be impedance-controlled (100 Ω differential) and length-matched to maintain the eye opening.
TI lists the SN65LVDS2DRG4 as Obsolete. Sourcing is through independent distribution and surplus channels. For new designs, the pin-compatible SN65LVDS2D (same 8-SOIC footprint, same 400 Mbps rating, active lifecycle) is the natural replacement — confirm the exact suffix and date code compatibility with your BOM.