At 400 Mbps the bit period is 2.5 ns, so the receiver's propagation delay and skew directly eat into the setup-and-hold budget. The SN65LVDS2DR is a receiver-only device (0 drivers, 1 receiver), so the link timing depends on the driver's edge rates and the interconnect's skew. In a typical 3.3 V backplane with FR-4 traces, the 400 Mbps rating gives enough headroom for a few inches of board trace plus a short cable segment. If the link runs longer than a few meters or passes through a connector with poor return loss, expect to derate the data rate or add pre-emphasis on the driver side.
On a mixed-voltage board where the FPGA core runs at 2.5 V and the I/O bank at 3.3 V, this receiver can sit on either rail as long as the common-mode input range is respected. Surface-mount assembly is standard — no special reflow profile needed beyond the usual lead-free recipe.
If a second source is needed for dual-sourcing discipline, the pin-compatible SN65LVDS2D (same die, different tape/reel suffix) is the obvious candidate — qualify the alternate now rather than during an allocation event.