LVDS fanout and signal routing in a 16-TSSOP
The Texas Instruments SN65LVDS22PWR is a 1 x 2:2 LVDS buffer and multiplexer in a 16-TSSOP package, designed to fan out or route one LVDS input to two LVDS outputs with minimal skew.
250 Mbps and 4.0 ns delay — timing budget considerations
At 250 Mbps, the 4.0 ns propagation delay adds directly to the total link latency. For a point-to-point LVDS link, this is usually absorbed in the setup/hold margin, but in a daisy-chained or repeated topology the accumulated delay can close the timing window. The 3 pF input capacitance is low enough to not load the upstream driver significantly, preserving signal integrity at the maximum data rate.