It handles serial data streams up to 250 Mbps with a propagation delay of 4.0 ns, making it suitable for clock distribution or data fan-out in point-to-point LVDS links. The 3 pF input capacitance keeps the load light on the driving source, and the 13 mA supply current at 3.3 V is typical for a single-channel LVDS fan-out buffer.
250 Mbps and 4.0 ns — timing budget for the serial link
The 250 Mbps data rate is the ceiling for NRZ signalling through this buffer. At that rate the bit period is 4 ns, and the 4.0 ns propagation delay consumes nearly one full bit period of the timing budget — so cascading multiple SN65LVDS22DG4 stages in a single link is not practical without reducing the line rate. For a single fan-out stage driving a 50 cm backplane trace to two receivers, the 4.0 ns delay plus the output transition time still leaves enough setup-and-hold margin for most LVDS receivers rated at 250 Mbps. If the design needs to run at 400 Mbps or higher, this part is not the right choice; look at a dedicated LVDS repeater with sub-2 ns delay.
The closest functional alternative is the SN65LVDS22 — the non-green/non-RoHS variant — but that part is also end-of-life.
16-SOIC footprint and 3.3 V rail
No separate core or I/O supply — the single 3.3 V pin powers both the input receiver and the output drivers.