LVDS fanout and signal routing for 250 Mbps links
The Texas Instruments SN65LVDS22D is a 1 x 2:2 LVDS buffer and multiplexer designed to fan out or route one differential LVDS input to two LVDS outputs.
Key parametric decisions for the BOM
The 250 Mbps data rate is the ceiling for each LVDS channel pair. The 4.0 ns delay is the propagation from input to output. Supply current is typically 13 mA, which is modest for a dual-output LVDS buffer. The 3 pF input capacitance is low enough to not load the driving source significantly at these speeds. The 1 x 2:2 configuration means one differential input is routed to two differential outputs — useful for splitting a single LVDS clock or data stream to two destinations without an external fanout buffer.
For a production BOM line, this means no imminent LTB risk and continued factory support from Texas Instruments.