PECL-to-LVDS signal conditioning in a 2×2 mm WSON
It is designed for high-speed serial links where signal integrity degrades across a backplane or long PCB trace — the reDriver cleans up the edge rates and re-drives the signal with LVDS levels. The part handles data rates up to 2 Gbps with a propagation delay of 460 ps, making it suitable for clock distribution and data repeater applications in telecom, networking, and industrial equipment.
460 ps delay — budget it into the timing closure
The 460 ps propagation delay is the time the reDriver adds from PECL input crossing to LVDS output transition. In a clock distribution chain, that delay must be accounted for in the overall skew budget — it is deterministic and part-to-part matched within the device, but it shifts the clock edge relative to a non-buffered path. For data repeaters at 2 Gbps (500 ps unit interval), the 460 ps delay consumes most of the bit period, so the part is best used as a point-to-point repeater rather than in a multi-drop configuration where cumulative delay would close the eye.