Texas Instruments SN65LVDS17DRFR, Buffer/ReDriver, Input PECL, Output LVDS, 4 Gbps max data rate, 460 ps delay, 40 mA supply, 2.375 V to 3.6 V supply, -40°C to 85°C, 8-WFDFN Exposed Pad package.
| Parameter | Value |
|---|---|
| Type | Buffer, ReDriver |
| Mounting | Surface Mount |
| Supply voltage | 2.375V ~ 3.6V |
| Current - supply | 40mA |
| Operating temperature | -40°C~85°C |
| Input | PECL |
| Output | LVDS |
| Package | Tape & Reel (TR); Cut Tape (CT) |
| Delay time | 460ps |
| Case | 8-WFDFN Exposed Pad |
| Data rate | 4Gbps |
| Channels | 1 |
At 4 Gbps the 460 ps delay is a fixed budget item in the link timing — you account for it in the total round-trip latency, not in the bit-period margin. The PECL input threshold is compatible with standard 3.3 V PECL levels, and the LVDS output drives 100 Ω differential lines directly. The single-channel configuration fits point-to-point links or one lane of a multi-lane bus where each channel needs its own re-driver.
The input is PECL (positive emitter-coupled logic) and the output is LVDS (low-voltage differential signaling).
The maximum data rate is 4 Gbps and the propagation delay is 460 ps.