LVDS serializer for high-speed parallel-to-serial conversion
The Texas Instruments SN65LVDS151DAR is a 10-input, 3-output LVDS serializer that converts 10 bits of parallel LVCMOS/LVTTL data into a 3-wire serial LVDS stream at rates up to 200 Mbps. It is designed for applications requiring low-jitter, high-throughput serial links over twisted-pair or PCB traces, such as flat-panel display interfaces, camera modules, and backplane data aggregation in industrial and telecom equipment.
The 200 Mbps per-channel serial data rate translates to an aggregate throughput of 600 Mbps across the three LVDS outputs. This is sufficient for uncompressed VGA video at 60 fps (roughly 150 Mbps raw pixel clock) or multiple lower-speed sensor streams. The serializer embeds the clock into the data stream, eliminating a separate clock pair and simplifying PCB routing. At this speed, signal integrity depends on controlled-impedance traces (typically 100 Ω differential) and keeping stub lengths under 0.5 inches.
10:3 channel mapping and LVDS I/O compatibility
The part accepts 10 parallel inputs from a host controller or image sensor (LVCMOS or LVTTL levels) and serializes them onto three LVDS output pairs. This 10:3 ratio is common in 18-bit or 24-bit RGB video links where three serial lanes carry pixel data, syncs, and control signals. The LVDS output swing (typically 350 mV differential) is compatible with standard LVDS receivers such as the SN65LVDS152 deserializer or any TIA/EIA-644 compliant receiver. The input threshold is set for LVTTL (1.5V typical), so 3.3V logic from an FPGA or MCU connects directly without level translation.
Package and footprint — 32-TSSOP tape-and-reel variant
The 32-TSSOP footprint is shared across the SN65LVDS151 family, so a board designed for the DAR variant can also accept the tube-packaged DA part without layout changes.