What this LVDS buffer/multiplexer does
The Texas Instruments SN65LVDS117DGGRG4 is a 1 x 2:16 LVDS buffer and multiplexer. It takes one LVDS input and fans it out to sixteen LVDS outputs, or selects between two input banks. This part is used in high-speed backplane routing, clock distribution, and data fan-out where signal integrity over twisted-pair or PCB traces matters. The 400 Mbps maximum data rate and 2.8 ns propagation delay set the timing budget for the link.
TI no longer manufactures this specific variant.
The 400 Mbps data rate per channel is the headline number — it tells you the maximum serial bit rate the LVDS outputs can sustain. For a 16-output fan-out, the aggregate throughput is 6.4 Gbps, but each output still runs at 400 Mbps. The 2.8 ns delay time matters for clock skew budgets: if you are distributing a 100 MHz clock, that 2.8 ns adds directly to the total skew between the input and the farthest output. The 5 pF input capacitance is low enough that a single LVDS source can drive the input without a repeater.
The SN65LVDS117DGGRG4 comes in a 64-TFSOP package (0.240", 6.10 mm width), also referred to as 64-TSSOP in the supplier device package field. It is a surface-mount, fine-pitch package — the 0.5 mm pin pitch typical of TSSOP-64. The G4 suffix indicates a lead-free, RoHS-compliant finish. For layout, the 64-TSSOP footprint is standard; decoupling capacitors near each supply pin pair are recommended, though the exact count depends on the board stack-up.